CS61318 Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS61318

E1 Line Interface Unit

Cirrus Logic 

CS61318

E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;

GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol Min

Typ

Max

TCLK Frequency

TCLK Duty Cycle

MCLK Frequency

RCLK Duty Cycle

Rise Time, All Digital Outputs

Fall Time, All Digital Outputs

TPOS/TNEG to TCLK Falling Setup Time

TCLK Falling to TPOS/TNEG Hold Time

RPOS/RNEG Valid Before RCLK Falling

RPOS/RNEG Valid Before RCLK Rising

RPOS/RNEG Valid After RCLK Falling

RPOS/RNEG Valid After RCLK Rising

ftclk

-

2.048

-

(Note12) tpwh2/tpw2

40

50

60

(Note 16) fmclk

-

2.048

-

(Note 17) tpwh1/tpw1

45

50

55

(Note 18)

tr

-

-

85

(Note 19)

tf

-

-

85

tsu2

25

-

-

th2

25

-

-

(Note 19) tsu1

100

194

-

(Note 20) tsu1

100

194

-

(Note 19)

th1

100

194

-

(Note 20)

th1

100

194

-

Units

MHz

%

MHz

%

ns

ns

ns

ns

ns

ns

ns

ns

Notes: 16. MCLK provided by an external source to TCLK.

17. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached.

18. At max load of 1.6mA and 50pF.

19. Host Mode (CLKE = 1).

20. Host Mode (CLKE = 0).

tr

tf

Any Digital Output

90%

10%

90%

10%

Figure 1. Signal Rise and Fall Characteristics

tpw1

RCLK

RPOS

RNEG

tpwl1

t su1

tpwh1

t h1

(CLKE = 1)

RCLK

(CLKE = 0)

Figure 2. Recovered Clock and Data Switching Characteristics

t pw2

t pwh2

TCLK

t su2

t h2

TPOS/TNEG

Figure 3. Transmit Clock and Data Switching Characteristics

6

DS441PP2

Share Link: