CS5126XD8 Просмотр технического описания (PDF) - ON Semiconductor

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CS5126XD8

High Performance, Integrated Current Mode PWM Controllers

ON Semiconductor 

CS5124, CS5126

APPLICATION INFORMATION

UVLO and Thermal Shutdown Interaction

0.82

The UVLO pin and thermal shutdown circuit share the

same internal comparator. During high temperature

operation (TJ > 100°C) the UVLO pin will interact with the

thermal shutdown circuit. This interaction increases the

turn–on threshold (and hysteresis) of the UVLO circuit. If

the UVLO pin shuts down the IC during high temperature

0.77

operation, higher hysteresis (see hysteresis specification)

might be required to enable the IC.

125°C

25°C

–40°C

BIAS Pin (CS5124 Only)

The bias pin can be used to control VCC as shown in the

main application diagram in Figure 1. In order to provide

adequate phase margin for the bias control loop, the pole

created by the series pass transistor and the VCC bypass

capacitor should be kept above 10 kHz. The frequency of

this pole can be calculated by Formula (1).

Transconductance of pass Transistor

Pole Frequency +

2 p CV(CC)

(1)

The Line BIAS pin shows a significant change in the

regulated VCC voltage when sinking large currents. This will

show up as poor line regulation with a low value pull–up

resistor. Typical regulated VCC vs BIAS pin sink current is

shown in Figure 3.

8.3

8.2

0.72

200 kHz

300 kHz

400 kHz

Frequency

500 kHz 600 kHz

Figure 4. CS5126 Maximum Duty Cycle vs. Frequency

(Synchronized Operation)

If the converter is initially free running and a sync signal

is applied, the current oscillator cycle will terminate and the

oscillator will lock on to the sync signal. The SYNC pin

works with a positive edge triggered signal. When the sync

signal transitions high the current PWM cycle terminates

and a new cycle begins as shown in Figure 5. The typical

phase lag between the rising edge of the SYNC signal and

the rising edge of the Gate is shown in Figure 6. When this

pin is held high or low the internal clock determines the

oscillator frequency.

SYNC

OSC

GATE

8.1

Figure 5. Synchronized Operation

8.0

140

7.9

5.0 µΑ 10 µΑ

20 µΑ

50 µΑ 100 µΑ 200 µΑ

Bias Current (IBIAS)

Figure 3. Regulated VCC vs. BIAS Sink Current

The BIAS pin and associated components form a high

impedance node. Care should be taken during PCB layout to

avoid connections that could couple noise into this node.

Clock Synchronization Pin (CS5126 Only)

The CS5126 can be synchronized to signals ranging from

30% slower to several times faster than the internal

oscillator frequency. If the part is synchronized to a fast

signal, maximum duty cycle will be reduced as the

frequency increases as shown in Figure 4.

130

120

110

100

90

80

70

200 kHZ

300 kHZ

400 kHZ 500 kHZ 600 kHZ

Figure 6. Typical Phase Lag between SYNC

and GATE on

http://onsemi.com

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