CS51033YN8 Просмотр технического описания (PDF) - Cherry semiconductor
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CS51033YN8 Datasheet PDF : 8 Pages
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Block Diagram
COSC
VCC
CS
VCC
IC
7IC
Oscillator
Comparator
A1
G1
VGATE
Flip-Flop
RQ
VC
RG
VGATE
1.5V
2.5V
F2
G2 S Q
VFB
Comparator
-
A6
1.25V
+
PGnd
VFB
VCC
IT
G4
G3
CS
Comparator
A2
+
Hold
Off
Comp
-
0.7V
-
Fault
Comp
+
1.15V
CS Charge
Sense
Comparator
A4
RQ
2.3V
IT
IT
55
5
1.5V
2.5V
F1
G5
SQ
Slow Discharge
Flip-Flop
A3
+ Slow Discharge
2.4V
Comparator
Gnd
Figure 1: Block Diagram for CS51033
Circuit Description
Theory of Operation
Control Scheme
The CS51033 monitors the output voltage to determine
when to turn on the PFET. If VFB falls below the internal ref-
erence voltage of 1.25V during the oscillator’s charge cycle,
the PFET is turned on and remains on for the duration of the
charge time. The PFET gets turned off and remains off dur-
ing the oscillator’s discharge cycle time with the maximum
duty cycle to 80%. It requires 7mV typical, and 20mV maxi-
mum ripple on the VFB pin is required to operate. This
method of control does not require any loop stability com-
pensation.
Startup
The CS51033 has an externally programmable soft start fea-
ture that allows the output voltage to come up slowly, pre-
venting voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT
source combination described by:
( ) ICS = IT -
IT
55
+
IT
5
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7V preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFB comparator’s (A6) ref-
erence input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the out-
put voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
4
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