PI74LCX543 Просмотр технического описания (PDF) - Pericom Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
PI74LCX543 Datasheet PDF : 5 Pages
| |||
PI74LCX543
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Fast CMOS 3.3V 8-Bit Latched Transceiver
Product Features
• Functionally compatible with FCT3, LVT, and 74
series 543 families of products
• Tri-State outputs
• 5V Tolerant inputs and outputs
• 2.0V-3.6V VCC supply operation
• Balanced sink and source output drives (24 mA)
• Low ground bounce outputs
• Supports live insertion
• ESD Protection exceeds 2000V, Human Body Model
200V, Machine Model
• Packages available:
– 24-pin 209-mil wide plastic SSOP (H)
– 24-pin 173-mil wide plastic TSSOP (L)
– 24-pin 150-mil wide plastic QSOP (Q)
– 24-pin 300-mil wide plastic SOIC (S)
Product Description
Pericom Semiconductor’s PI74LCX series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LCX543 is an 8-bit wide non-inverting transceiver designed
with two sets of eight D-type latches with separate input and output
controls for each set. For data flow from A to B, for example, the
A-to-B Enable (CEAB) input must be LOW in order to enter data
from A0–A7 or to take data from B0–B7, as indicated in the Truth
Table. With CEAB LOW, a LOW signal makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the LEAB
signal puts the A latches in the storage mode and their outputs no
longer change the A inputs. With CEAB and OEAB both LOW, the
3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but
uses the CEAB, LEAB, and OEAB inputs.
The PI74LCX543 can be driven from either 3.3V or 5.0V devices
allowing this device to be used as a translator in a mixed
3.3/5.0V system.
Logic Block Diagram
DQ
LE
A0
A1
A2
A3
A4
A5
A6
A7
OEBA
CEBA
LEBA
QD
LE
DETAIL A x 7
1
B0
B1
B2
B3
B4
B5
B6
B7
OEAB
CEAB
LEAB
PS2102A 02/25/97
Share Link: 