AFBR-5803AQZ Просмотр технического описания (PDF) - Avago Technologies

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AFBR-5803AQZ

FDDI, 100 Mb/s ATM, and Fast Ethernet Transceivers in Low Cost 1 x 9 Package Style

Avago Technologies 

-2

1 x 10

-3

1 x 10

-4

1 x 10

-5

1 x 10

-6

1 x 10

-7

1 x 10-8

1 x 10-9

1 x 10

1 x 10-10

1 x 10-11

1 x 10-12

AFBR-5803 SERIES

CENTER OF SYMBOL

-6 -4

-2

0

2

4

RELATIVE INPUT OPTICAL POWER - dB

CONDITIONS:

1. 155 MBd

2. PRBS 27-1

3. CENTER OF SYMBOL SAMPLING

4. TA = +25˚C

5. VCC= 3.3 V to 5 V dc

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.

Rx

Tx

NO INTERNAL CONNECTION

NO INTERNAL CONNECTION

AFBR-5803

TOP VIEW

Rx

Rx Tx

Tx

VEE

RD RD

SD

VCC

VCC

TD

TD VEE

1

2

3

4

5

6

7

8

9

Transceiver Jitter Performance

The Avago Technologies 1300 nm transceivers are

designed to operate per the system jitter allocations

stated in Tables E1 of Annexes E of the FDDI PMD and

LCF-PMD standards.

The Avago Technologies 1300 nm transmitters will

tolerate the worst case input electrical jitter allowed in

these tables without violating the worst case output jitter

requirements of Sections 8.1 Active Output Interface of

the FDDI PMD and LCF-PMD standards.

The Avago Technologies 1300 nm receivers will tolerate

the worst case input optical jitter allowed in Sections 8.2

Active Input Interface of the FDDI PMD and LCF-PMD

standards without violating the worst case output electri-

cal jitter allowed in the Tables E1 of the Annexes E.

The jitter specifications stated in the following 1300 nm

transceiver specification tables are derived from the

values in Tables E1 of Annexes E. They represent the worst

case jitter contribution that the trans­ceivers are allowed

to make to the overall system jitter without violating the

Annex E allocation example. In practice the typical con-

tribution of the Avago Technologies trans­ceivers is well

below these maximum allowed amounts.

TERMINATION

AT PHY

DEVICE

INPUTS

VCC

R5 R7

C6

R6

R8

C1

C2

L1 L2

C3

C4

VCC FILTER

AT VCC PINS

TRANSCEIVER

R9

R10

VCC

R2 R3

R1

R4

C5

TERMINATION

AT TRANSCEIVER

INPUTS

RD RD SD

VCC

TD

TD

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.

R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

C4 = 10 µF.

L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.

Figure 7. Recommended Decoupling and Termination Circuits



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