ADP3208C Просмотр технического описания (PDF) - ON Semiconductor
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ADP3208C Datasheet PDF : 37 Pages
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ADP3208C
ELECTRICAL CHARACTERISTICS VCC = PVCC1 = PVCC2 = BST1 = BST2 = High = 5.0V, FBRTN = GND = SW1 = SW2 = PGND1
= PGND2 = Low = 0 V, EN = VATFREQ = High, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = −40°C to 100°C, unless otherwise
noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min Typ Max Unit
VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)
FB, LLINE Voltage Range
(Note 2)
VFB, VLLINE Relative to CSREF = VDAC
−200
+200 mV
FB, LLINE Offset Voltage
(Note 2)
VOSVEA
Relative to CSREF = VDAC
−0.5
+0.5
mV
FB LLINE Bias Current
IFB
(Note 2)
−100
100
A
LLINE Positioning Accuracy
VFB − VVID
Measured on FB relative to VVID, LLINE
forced 80 mV below CSREF
−78
−80
−82
mV
COMP Voltage Range
COMP Current
VCOMP
ICOMP
Operating Range
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
0.85
4.0
V
mA
−0.75
6.0
COMP Slew Rate
SRCOMP
CCOMP = 10 pF, CSREF = VDAC,
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
V/ms
15
−20
Gain Bandwidth (Note 2)
GBW
VID DAC VOLTAGE REFERENCE
Non−inverting unit gain configuration,
RFB = 1 kW
20
MHz
VDAC Voltage Range (Note 3)
See VID Code Table
0
1.5
V
VDAC Accuracy
VFB − VVID
Measured on FB (includes offset),
relative to VVID, for VID table see Table 3,
VVID = 1.2125 V to 1.5000 V
VVID = 0.3000 V to 1.2000 V
−9.0
−7.5
mV
+9.0
+7.5
VDAC Differential Non−linearity (Note 2)
−1.0
+1.0 LSB
VDAC Line Regulation
DVFB
VCC = 4.75 V to 5.25 V
0.05
%
VDAC Boot Voltage (Note 2)
VBOOTFB
Measured during boot delay period
1.200
V
Soft−Start Delay (Note 2)
tDSS
Measured from EN pos edge to FB = 50 mV
200
ms
Soft−Start Time
tSS
Measured from EN pos edge to FB settles to
1.7
ms
VBOOT = 1.2 V within −5%
Boot Delay
tBOOT
Measured from FB settling to VBOOT = 1.2 V
150
ms
within −5% to CLKEN neg edge
VDAC Slew Rate
Soft−Start
Non−LSB VID step, DPRSLP = H,
Slow C4 Entry/Exit
Non−LSB VID step, DPRSLP = L,
Fast C4 Exit
0.0625
0.25
1.0
LSB/ms
FBRTN Current
IFBRTN
VOLTAGE MONITORING AND PROTECTION − Power Good
90
200
mA
CSREF Undervoltage
Threshold
VUVCSREF
Relative to DAC Voltage:
= 0.5 V to 1.5 V
mV
−360 −300 −240
= 0.3 V to 0.4875 V −360 −300 −160
CSREF Overvoltage
Threshold
VOVCSREF
Relative to nominal DAC Voltage
150
200
250
mV
CSREF Crowbar Voltage
Threshold
VCBCSREF
Relative to FBRTN
1.57
1.7
1.78
V
CSREF Reverse Voltage
Threshold
VRVCSREF
Relative to FBRTN, Latchoff mode:
CSREF Falling
CSREF Rising
mV
−350 −300
−70 −5.0
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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