AD74322DAR Просмотр технического описания (PDF) - Analog Devices
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AD74322DAR Datasheet PDF : 20 Pages
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AD74322
PRELIMINARY TECHNICAL DATA
BCLK/
SCLK
LRCLK/
FS
DSDATA/
SDI
ASDATA/
SDO
CONTROL
STATUS
LEFT DAC
LEFT ADC
RIGHT DAC
RIGHT ADC
Figure <DSP_Protocol>
INARY DSP
IM AL (MASTER)
TFS
DT
SCLK
DR
RFS
AD743xx
(SLAVE)
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
SDOFS
REL NIC Figure <Data_DSP_Master>
P H Theserialprotocolusesafixedpositionfordatabeingsenttoorreceived
C A fromtheLeftandRightDACsandADCsrespectivelyandthecontrol
E T wordsbeingsenttoandthestatuswordsbeingreceivedfromthedevice
T DA respectively.Figure<DSP_Protocol>detailsthearrangementofboth
ADSP-
21065L
(MASTER)
TFS
DT
TCLK
DR
RFS
RCLK
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
Figure <Data_I2S_DSP_Master>
TFS
LRCLK/SDIFS
audio and control/status information in the serial transfer.
I2S(InterICSoundBus)Mode
The I2S bus is a three line serial bus which features a serial data line
ADSP-
21065L
(MASTER)
DT
TCLK
DR
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
carrying both left and right (stereo) channels. The Left and Right channel
RFS
AD743xx
information are selected by the status of the Left/Right Clock (Word
Select) line. Serial data is clocked by the Bit Clock line. Figures
RCLK
(SLAVE)
<Data_I2S_DSP_Master> and <Data_I2S_DSP_Slave> detail the
interface configuration between controller and codec in I2S mode with
controller as master and slave respectively. Figure <> details I2S timing.
Figure <Data_I2S_DSP_Slave>
The interface allows easy transfer of arbitrary length serial data samples
sent MSB first. Toggling of the Left/Right Clock line indicates that the
end of the current word will occur after the following Bit Clock cycle and
the start of the alternate channel word will occur on the subsequent Bit
Clock cycle
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
I2S MODE - 16 TO 24-BITS PER CHANNEL
Figure <I2S_Timing>
–12–
LSB
Pr D 03/00
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