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AD6620S/PCB

67 MSPS Digital Receive Signal Processor

Analog Devices 

TIMING DIAGRAMS

CLK, INPUTS, PARALLEL OUTPUTS

RESET with PAR/SER = “1” establishes Parallel Outputs active.

SYNC PULSES: SLAVE OR MASTER

AD6620

t CLK

t CLKH

CLK

t CLKL

Figure 3. CLK Timing Requirements

CLK

t SI

t HI

IN[15:0]

EXP[2:0]

A/B

DATA

Figure 4. Input Data Timing Requirements

t DPR

t DPF

t DPF

CLK

DVOUT

VALID OUTPUT DATA

I/QOUT

I

Q

I

Q

OUT[15:0]

IA

QA

IB

QB

Figure 5. Parallel Output Switching Characteristics

CLK

SYNC NCO

SYNC CIC

SYNC RCF

t SY

t HY

NOTE:

IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH

OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL

CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK

CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL

BE INHIBITED AND NOT INCREMENT PROPERLY.

Figure 6. SYNC Slave Timing Requirements

CLK

t CLK

t CHP

IN[15:0]

E[2:0]

t CS

N

t CPL

t CH

N+1

A/B

Figure 7. SYNC Master Delay

RESET

t RESL

Figure 8. Reset Timing Requirements

REV. A

–7–

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