82374EB Просмотр технического описания (PDF) - Intel

Номер в каталоге

Компоненты Описание

Список матч

82374EB

EISA SYSTEM COMPONENT (ESC)

Intel 

82374EB 82374SB

PCI Bus Arbitration

The PCI arbiter supports six PCI masters The Host PCI bridge PCEB and four other PCI masters The

arbiter can be programmed for twelve fixed priority schemes a rotating scheme or a combination of the fixed

and rotating schemes The arbiter can be programmed for bus parking that permits the Host PCI Bridge

default access to the PCI Bus when no other device is requesting service The arbiter also contains an efficient

PCI retry mechanism to minimize PCI Bus thrashing when the PCEB generates a retry The arbiter can be

disabled if an external arbiter is used

EISA Bus Interface

The PCEB contains a fully EISA-compatible master and slave interface The PCEB directly drives eight EISA

slots without external data or address buffering The PCEB is only a master or slave on the EISA Bus for

transfers between the EISA Bus and PCI Bus For transfers contained to the EISA Bus the PCEB is never a

master or slave However the data swap logic contained in the PCEB is involved in these transfers if data size

translation is needed The PCEB also provide support for I O recovery

EISA ISA masters and DMA can access PCI memory or I O The PCEB only forwards EISA cycles to the PCI

Bus if the address of the transfer matches one of the address ranges programmed into the PCEB for EISA-to-

PCI positive decode This includes the main memory segments used for generating MEMCS from the EISA

Bus one of the four programmable memory regions or one of the four programmable I O regions For EISA-

initiated accesses to the PCI Bus the PCEB is a slave on the EISA Bus I O accesses are always non-buffered

and memory accesses can be either non-buffered or buffered via the Line Buffers For buffered accesses

burst cycles are supported

During PCI-initiated cycles to the EISA Bus the PCEB is an EISA master For memory write operations through

the Posted Write Buffers the PCEB uses EISA burst transfers if supported by the slave to flush the buffers

Otherwise single cycle transfers are used Single cycle transfers are used for all I O cycles and memory

reads

PCI EISA Address Decoding

The PCEB contains two address decoders one to decode PCI-initiated cycles and the other to decode EISA-

initiated cycles The two decoders permit the PCI and EISA Buses to operate concurrently

The PCEB can also be programmed to provide main memory address decoding on behalf of the Host PCI

bridge When programmed the PCEB monitors the PCI and EISA bus cycle addresses and generates a

memory chip select signal (MEMCS ) indicating that the current cycle is targeted to main memory residing

behind the Host PCI bridge Programmable features include read write attributes for specific memory seg-

ments and the enabling disabling of a memory hole If MEMCS is not used this feature can be disabled

In addition to the main memory address decoding there are four programmable memory regions and four

programmable I O regions for EISA-initiated cycles EISA ISA master or DMA accesses to one of these

regions are forwarded to the PCI Bus

Data Buffering

To isolate the slower EISA Bus from the PCI Bus the PCEB provides two types of data buffers Buffer

management control guarantees data coherency

For EISA-initiated cycles to the PCI Bus there are four 16-byte wide Line Buffers These buffers permit

prefetching of PCI memory read data and posting of PCI memory write data

15

Share Link: