DS1077(2003) Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1077 Datasheet PDF : 21 Pages
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DS1077
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(-40°C to +85°C; VCC= 5V±5%)
PARAMETER
SYMBOL CONDITION MIN TYP MAX UNITS NOTES
SCL Clock Frequency
fSCL
Fast Mode
Standard Mode
400 kHz
100
Bus Free Time
tBUF
Fast Mode
1.3
µs
Between a STOP
Standard Mode
4.7
and START Condition
Hold Time (Repeated)
tHD:STA
Fast Mode
0.6
START Condition
Standard Mode
4.0
µs
6
LOW Period of SCL
tLOW
Fast Mode
1.3
µs
Standard Mode
4.7
HIGH Period of SCL
tHIGH
Fast Mode
0.6
µs
Standard Mode
4.0
Set-Up Time for a
tSU:STA
Fast Mode
0.6
µs
Repeated START
Standard Mode
4.7
Data Hold Time
tHD:DAT
Fast Mode
0
Standard Mode
0
0.9
µs
7,8
Data Set-Up Time
tSU:DAT
Fast Mode
100
ns
Standard Mode 250
Rise Time of Both
SDA and SCL Signals
tR
Fast Mode
Standard Mode
20 + 0.1CB
300 ns
9
1000
Fall Time of Both SDA
and SCL Signals
tF
Fast Mode
Standard Mode
20 + 0.1CB
300 ns
9
Set-Up Time For STOP
tSU:STO
Fast Mode
0.6
µs
Standard Mode
4.0
Capacitive Load for
CB
Each Bus Line
400 pF
9
Input Capacitance
CI
5
pF
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER
SYMBOL CONDITION MIN
Writes
+85°C
10,000
TYP MAX UNITS NOTES
NOTES:
1) All voltages are referenced to ground.
2) 8.13kHz is obtained from a -66MHz standard part.
3) PDN is a power-down signal applied to either CTRL0 or CTRL1 pins as appropriate.
4) Output voltage swings may be impaired at high frequencies combined with high output loading.
5) After this period, the first clock pulse is generated.
6) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7) The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
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