CS5471 Просмотр технического описания (PDF) - Cirrus Logic

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CS5471

Dual-Channel Delta-Sigma Analog-to-Digital Converter

Cirrus Logic 

CS5471

3. PIN DESCRIPTION

Serial Clock Output

SCLK

Serial Data Output

SDO

Frame Sync

FSO

Serial Port Enable

SE

Current Input Gain

GAIN

Analog Ground AGND

Reference Input VREFIN

Reference Output VREFOUT

Positive Analog Supply

VA+

Negative Analog Supply

VA-

1

20 VD+

Digital Supply

2

19 DGND Digital Ground

3

18 CPD

Charge Pump Drive

4

17 XIN

Master Clock

5

16 RESET Reset

6

15 OWRS Output Word Rate Select

7

14 VIN+

Differential Voltage Input 1

8

13 VIN-

Differential Voltage Input 1

9

12 IIN+

Differential Current Input 1

10 11 IIN-

Differential Current Input 1

Clock Generator

XIN - Master Clock Input

Control Pins and Serial Data I/O

SE - Serial Port Enable.

When SE is low, the output pins of the serial port are 3-stated.

SDO - Serial Port Output.

Data will be at a rate determined by SCLK.

FSO - Frame Signal Output.

Framing signal output for data transfer from SDO pin.

SCLK - Serial Clock Output.

A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined

by XIN frequency and state of OWRS input pin.

RESET - Reset.

When reset is taken low, all internal registers are set to their default states.

GAIN - Input Gain Control.

Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to

20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor

to DGND).

OWRS - Output Word Rate Select.

When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to

logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will

default to logic low level (through internal 200K resistor to DGND).

11

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