ST16C2450CJ44 Просмотр технического описания (PDF) - Exar Corporation

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ST16C2450CJ44

2.97V TO 5.5V DUART

Exar Corporation 

xr

REV. 4.0.1

ST16C2450

2.97V TO 5.5V DUART

Pin Description

NAME

44-PLCC

PIN #

48-TQFP

PIN #

TYPE

DESCRIPTION

ANCILLARY SIGNALS

XTAL1

18

13

I Crystal or external clock input.

XTAL2

19

14

O Crystal or buffered clock output.

RESET

39

36

I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will

reset the internal registers and all outputs. The UART transmitter output

will be held at logic 1, the receiver input will be ignored and outputs are

reset during reset period.

VCC

44

42

Pwr 2.97V to 5.5V power supply. All inputs are 5V tolerant for devices with

top marking of "A2 YYWW" and newer.

GND

22

17

Pwr Power supply common, ground.

N.C.

1, 12, 23, 6, 12, 18,

- No Connection. These pins are open, but typically, should be con-

34

24, 25, 31,

nected to GND for good design practice.

37, 43

Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.

1.0 PRODUCT DESCRIPTION

The ST16C2450 (2450) integrates the functions of two 16C450 Universal Asynchrounous Receiver and

Transmitter (UART). Each UART is independently controlled having its own set of device configuration

registers. The 2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-

parallel data conversions for both the transmitter and receiver sections. These functions are necessary for

converting the serial data stream into parallel data that is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.

The 2450 represents such an integration with greatly enhanced features. The 2450 is fabricated with an

advanced CMOS process. The 2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a crystal

or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The 2450 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share

the same data bus for host operations. The data bus interconnections are shown in Figure 3.

5

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