IS61VPD25636A-250B3 Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS61VPD25636A-250B3

256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STaTIC RaM

Integrated Silicon Solution 

IS61VPD25636a IS61LPD25636a

IS61VPD51218a IS61LPD51218a

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INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

LINEAR BURST ADDRESS TABLE (MODE = Vss)

0,0

A1', A0' = 1,1

0,1

   

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter

Value

Unit

Tstg

Storage Temperature

–55 to +150

°C

Pd

Power Dissipation

1.6

W

Iout

Output Current (per I/O)

100

mA

Vin, Vout Voltage Relative to Vss for I/O Pins

–0.5 to Vddq + 0.5 V

Vin

Voltage Relative to Vss for

for Address and Control Inputs

–0.5 to Vdd + 0.5 V

Vdd

Voltage on Vdd Supply Relative to Vss

–0.5 to 4.6

V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages

or electric fields; however, precautions may be taken to avoid application of any voltage

higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc. — 1-800-379-4774

11

Rev. C1

05/31/2017

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