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CS5132GDW24

Dual Output CPU Buck Controller

Cherry semiconductor 

Electrical Characteristics: 0ûC < TA < 70ûC; 0ûC < TJ < 125ûC; VOUT2 3.5V, 9V VCC1 14V, 9V VCC2 14V; 2.0V DAC Code

(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.

PARAMETER

TEST CONDITIONS

s VI/O Switching Regulator Error Amplifier continued

Unity Gain Bandwidth

CCOMP2 = 0.1µF

PSRR @ 1kHZ

CCOMP2 = 0.1µF

Reference Voltage

VFB2=COMP2

s GATE

High Voltage at 100mA

Low Voltage at 100mA

Rise Time

Fall Time

GATE pull-down

Measure VCC2 ÐGATE

Measure GATE

1.6V < GATE < (VCC2 Ð 2.5V)

(VCC2 Ð 2.5V) > GATE > 1.6V

Resistance to PGnd

MIN

TYP

MAX

UNIT

1.205

20

70

1.230

1.255

KHz

dB

V

1.2

2.1

V

1.0

1.5

V

40

80

ns

40

80

ns

20

50

115

k½

s VI/O Overcurrent Protection

OVC2 Comparator Offset Voltage 0V < VOUT2 ² 3.5V

Discharge Threshold Voltage

VOUT2 Bias Current

OVC2 Latch Discharge Current

0.2V ² VOUT2 ² 3.5V

77

86

101

mV

0.2

0.25

0.3

V

-7.0

0.1

7.0

µA

100

800

2500

µA

s PWM Comparator 2

PWM Comparator Offset Voltage 0V ² VFFB2 ² 3.5V

Transient Response

VFFB2 = 0 to 3.5V

VFFB2 Bias Current

0.2V ² VFFB2 ² 3.5V

s COFF2

Off-Time

Charge Current

Discharge Current

VCOFF2 = 1.5V

VCOFF2 = 1.5V

s General Electrical Specifications

VCC Monitor Start Threshold

VCC Monitor Stop Threshold

Hysteresis

All Outputs On

All Outputs Off

Start - Stop

VCC1 Supply Current

VCC2 Supply Current

No Load on GATE(L)

No Loads on GATE(H) and GATE

Note 1: Guaranteed by design, not 100% tested in production.

0.99

1.10

1.22

V

200

300

ns

-7.0

0.1

7.0

µA

1.0

1.6

2.3

µs

550

µA

25

mA

7.9

8.4

8.9

V

7.6

8.1

8.6

V

0.15

0.30

0.60

V

13

20

mA

6

9

mA

6

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