TDA7503(1999) Просмотр технического описания (PDF) - STMicroelectronics

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TDA7503
(Rev.:1999)

DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

STMicroelectronics 

TDA7503

POWER CONSUMPTION

Symbol

Ptot

Parameter

Maximum current for core power supply @ 3.3V

Note: 40MHz internal DSP clock at Tamb

Value

320

Unit

mA

EXTERNAL CLOCKS (XTI Pin)

The TDA7503 system clock is externally supplied via the XTI pin.

Timings shown in this document are valid for clock rise and fall times of 3ns maximum.

Symbol

Characteristics

Fext Max. Frequency @ XTI when PLL is disabled

When PLL is enabled see constraints for Internal Clocks.

Value

20

Unit

MHz

INTERNAL CLOCKS

Symbol

fDSP_MAX

fµP_MAX

fDSP

fµP

Icyc_DSP

Icyc_µP

Characteristics

Maximum DSP Internal Operation Frequency (dclk)

Maximum µP (8051) Internal Operation Frequency (mclk)

Internal DSP Clock Cycle Frequency (dclk)

Inernal µP (8051) Clock Cycle Frequency (mclk)

DSP Machine Cycle Time

µP (8051) Machine Cycle Time

Expression

40MHz

20MHz

MF ⋅ Fext

2 ⋅ DF

MF ⋅ Fext

4 ⋅ DF

dclk

mclk/12

Note 1: If the DCKSRC bit of the clock control register is 0 then dclk = Fext/2.

Note 2: If the MCKSRC bit of the clock control register is 1 then mclk = Fext else of MCKSRC0 is 0 then MCLK = Fext/4.

Note 3: DF is PLL input devide factor, bits IDF [4:0] of PLL control register one.

Note 4: MF is PLL multiply devide factor, bits MP [6:0] of PLL control register zero.

PHASE LOCKED LOOP (PLL) CHARACTERISTICS

Characteristics

VCO frequency when PLL enabled

Recommended PLL external capacitor (pin

FILT)

Expression

MF ⋅ Fext

DF

RESET

Characteristics

Minimum RESET assertion

Expression

100/Fext

Value

40 to 80

3.3

Unit

MHz

nF

Unit

ns

9/26

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