74HC4520 Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC4520 Datasheet PDF : 17 Pages
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Nexperia
74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Q4
Q4
Q4
Q4
Q&3
Q&3
Q05
4
))
&3
5' 4
Fig 3. Logic diagram for one counter
6. Pinning information
6.1 Pinning
4
))
&3
5' 4
4
))
&3
5' 4
4
))
&3
5' 4
DDD
+&
+&7
&3
&3
4
4
4
4
05
*1'
9&&
05
4
4
4
4
&3
&3
DDD
Fig 4. Pin configuration SO16
+&
+&7
&3
&3
4
4
4
4
05
*1'
9&&
05
4
4
4
4
&3
&3
DDD
Fig 5. Pin configuration TSSOP16 and SSOP16
6.2 Pin description
Table 2. Pin description
Symbol
1CP0, 2CP0
1CP1, 2CP1
1Q0 to 1Q3
1MR, 2MR
GND
2Q0 to 2Q3
VCC
Pin
1, 9
2, 10
3, 4, 5, 6
7, 15
8
11, 12, 13, 14
16
Description
clock input (LOW-to-HIGH edge-triggered)
clock input (HIGH-to-LOW edge-triggered)
output
asynchronous master reset input (active HIGH)
ground (0 V)
output
supply voltage
74HC_HCT4520
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 May 2016
© Nexperia B.V. 2017. All rights reserved
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