74HC75D Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC75D Datasheet PDF : 20 Pages
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Philips Semiconductors
74HC75
Quad bistable transparant latch
3. Quick reference data
Table 1: Quick reference data
Symbol Parameter
Conditions
Min Typ Max Unit
tPHL, tPLH propagation delay
nD to nQ, nQ
CL = 15 pF;
VCC = 5 V
-
11
-
ns
LEnn to nQ, nQ
-
11
-
ns
CI
input capacitance
-
3.5 -
pF
CPD
power dissipation
VI = GND to VCC [1] -
42
-
pF
capacitance per latch
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2: Ordering information
Type number Package
Temperature range
74HC75N
−40 °C to +125 °C
74HC75D
−40 °C to +125 °C
74HC75DB
−40 °C to +125 °C
74HC75PW
−40 °C to +125 °C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
9397 750 13816
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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