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74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

NXP Semiconductors. 

Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

6. Functional description

Table 3. Function table[1]

Operating Input

Output

modes

MR

CP

CEP

CET

PE

Dn

Qn

TC

Reset (clear) L

X

X

X

X

X

L

L

Parallel load H

↑

X

X

l

l

L

L

H

↑

X

X

l

h

H

[2]

Count

H

↑

h

h

h

X

count

[2]

Hold

H

X

l

X

h

X

qn

[2]

(do nothing) H

X

X

l

h

X

qn

L

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition

qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition

X = don’t care

↑ = LOW-to-HIGH clock transition

[2] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)

0

1

2

3

4

15

5

14

6

13

7

Fig. 7. State diagram

12

11

10

9

8

aaa-012187

74HC161

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 4 October 2018

© Nexperia B.V. 2018. All rights reserved

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