74HC161(2017) Просмотр технического описания (PDF) - NXP Semiconductors.

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74HC161
(Rev.:2017)

Presettable synchronous 4-bit binary counter; asynchronous reset

NXP Semiconductors. 

NXP Semiconductors

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 14.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min

Max

Min

Max

CPD

power

VI = GND to VCC; VCC = 5 V; [3] -

33

-

-

dissipation fi = 1 MHz

capacitance

-

-

- pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W):

PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CL  VCC2  fo) = sum of outputs.

11. Waveforms

9,

&3LQSXW

*1'

92+

4Q7&

RXWSXW

92/

IPD[

90

W:

W3+/



90



W7+/

W3/+





W7/+

DDD

Fig 9.

Measurement points are given in Table 8.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum

frequency

74HC161

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 4 January 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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