72V275L10PF(2018) Просмотр технического описания (PDF) - Integrated Device Technology

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72V275L10PF
(Rev.:2018)

3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18

Integrated Device Technology 

IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM

32,768 x 18 and 65,536 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Figure 4, Programmable Flag Offset Programming Sequence, summa- Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter

rizes the control pins and sequence for both serial and parallel programming Master Reset, regardless of whether serial or parallel programming has been

modes. For a more detailed description, see discussion that follows.

selected.

TABLE 1. STATUS FLAGS FOR IDT STANDARD MODE

72V275

72V285

Number of

Words in

FIFO

0

1 to n (1)

(n+1) to 16,384

16,385 to (32,768-(m+1))

(32,768-m) (2) to 32,767

32,768

0

1 to n (1)

(n+1) to 32,768

32,769 to (65,536-(m+1))

(65,536-m) (2) to 65,535

65,536

FF PAF HF PAE EF

H HH L L

H HH L H

H HH H H

H HL H H

H LL H H

L LL H H

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

TABLE 2. STATUS FLAGS FOR FWFT MODE

72V275

72V285

IR PAF HF PAE OR

Number of

Words in

FIFO

0

1 to n+1(1)

(n+2) to 16,385

16,386 to (32,769-(m+1)) (2)

(32,769-m) to 32,768

32,769

0

1 to n+1(1)

(n+2) to 32,769

32,770 to (65,537-(m+1)) (2)

(65,537-m) to 65,536

65,537

L HH LH

L HH L L

L HH H L

L HL H L

LLL HL

HL L H L

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

4512 drw 05

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