SCC2691AC1N24,602 Просмотр технического описания (PDF) - NXP Semiconductors.
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SCC2691AC1N24,602 Datasheet PDF : 25 Pages
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Philips Semiconductors
Universal asynchronous receiver/transmitter (UART)
Product data sheet
SCC2691
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
SYMBOL
Reset timing (Figure 3)
PARAMETER
LIMITS
UNIT
Min
Typ
Max
tRES
Reset pulse width
Bus timing (Figure 4)5
100
ns
tAS
A0–A2 setup time to RDN, WRN low
tAH
A0–A2 hold time from RDN, WRN low
tCS
CEN setup time to RDN, WRN low
tCH
CEN hold time from RDN, WRN high
tRW
WRN, RDN pulse width
tDD
Data valid after RDN low
tDF
Data bus floating after RDN high
tDS
Data setup time before WRN high
tDH
Data hold time after WRN high
tRWD
Time between reads and/or writes6, 7
MPI and MPO timing (Figure 5)5
10
ns
100
ns
0
ns
0
ns
150
ns
125
ns
110
ns
50
ns
30
ns
150
ns
tPS
MPI input setup time before RDN low
tPH
MI input hold time after RDN low
tPD
MPO output valid after WRN high
Interrupt timing (Figure 6)
30
ns
30
ns
370
ns
tIR
INTRN negated
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY, TxEMT interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
Clock timing (Figure 7)
370
ns
370
ns
370
ns
370
ns
370
ns
270
ns
tCLK
fCLK9
tCTC
fCTC8
tRX
fRX8
tTX
fTX8
X1/CLK high or low time
X1/CLK frequency
Counter/timer clock high or low time
Counter/timer clock frequency
RxC high or low time
RxC frequency (16X)
RxC frequency (1X)
TxC high or low time
TxC frequency (16X)
TxC frequency (1X)
100
ns
0
4.0
MHz
100
ns
0
4.0
MHz
220
ns
0
3.6864
2.0
MHz
0
1.0
MHz
220
ns
0
2.0
MHz
0
1.0
MHz
Transmitter timing (Figure 8)
tTXD
TxD output delay from TxC external clock input on IP pin
tTCS
Output delay from TxC low at OP pin to TxD data output
0
Receiver timing (Figure 9)
350
ns
150
ns
tRXS
RxD data setup time before RxC high at external clock input on IP pin
100
ns
tRXH
RxD data hold time after RxC high at external clock input on IP pin
100
ns
NOTES:
1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and VCC supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must
be negated for tRWD guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes.
8. These parameters are guaranteed by design, but are not 100% tested in production.
9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
2006 Aug 04
6
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