L6452(1999) Просмотр технического описания (PDF) - STMicroelectronics
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L6452 Datasheet PDF : 16 Pages
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L6452
DC ELECTRICAL CHARACTERISTICS (Tj = 25°C)
Symbol
Parameter
A/D CONVERTER TIMINGS
Tcscks
Conv. start set up time
T csckh
Conv. Start hold time
Tckou t
Falling edge of clock to data
out valid delay
Tcsz
ConvStart falling edge to output
in Hi-Z delay
Fadck
Clock frequency
Tcslow
Conv. Start low level time
Tacq th
Theoretical acquisition time
Tacq pr
Real acquisition time
DIGITAL INTERFACE INPUT
Vinp
Schmitt Trigger positive-going
Threshold
Vinm
Schmitt Trigger negative-going
Threshold
Vh ys
Scmitt Trigger Hysteresis
Iin
Input Current (Vin=0; Vdd=5)*
Test Condition
Cload ≤ 20pF
fadck = 250 kHz
fadck = 250 kHz
Min. Typ.
200
200
5.6
32.4
36
1/3Vdd
0.1
0.3
50
150
* This applies to input pins having an internal pull-up (ENABLE_CHANNEL, LONG_PULSE, SHORT_PULSE)
Max.
200
200
250
2/3Vdd
1
300
Unit
ns
ns
ns
ns
KHz
µs
µs
µs
V
V
V
µA
CR LATCH TIMINGS
Tls
Latch set up time
100
ns
Tlhigh
Latch high time
100
ns
Tlconv
Latch data valid to A/D input
Selected channel:
valid delay
CH1..CH5
4
µs
CH0
7
µs
NB: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the
data 16 bit shift register (signals Serial data, Serial clock)
SHIFT REGISTER AND LATCH TIMING
Ta
Set up time
Tb
Hold time
Tc
Serial clock low time
Td
Serial clock high time
Te
Serial clock period
Tf
Latch set up time
50
ns
50
ns
50
ns
50
ns
150
ns
100
ns
Tg
Latch data high time
100
ns
Tset
Long Pulse set_up time with
respect to NCEn
160
ns
Thold
Long Pulse hold time with
respect to NCEn
0
ns
OUTPUTS ELECTRICAL CHARACTERISTICS
Io ut
Output Current (outputs 0..15) DC=33%;
preheating DC=66%
400
mA
Rds (ON)
Ton
On Resistance
Turn on Time (Tdelay + Trise)
Tj = 25°C
From 50% Long Pulse to 90%
power output rising edge
Load = 30 Ohm in parallel with
1.5nF
1.3
Ω
160
ns
Toff
Toff delay time
From 50% Long Pulse to 90%
power output falling edge
Load = 30 Ohm in parallel with
1.5nF
100
ns
7/16
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