Figure 9. Immediate Read Sequence and Timing
N
BUS ACTIVITY: S
O
T
S
A
SLAVE
AT
MASTER R ADDRESS
CO
T
KP
S
P
SLAVE
A
C
DATA
K
BYTE
CAT24C164
SCL
SDA
8
8th Bit
DATA OUT
9
NO ACK
STOP
Figure 10. Selective Read Sequence
N
BUS ACTIVITY: S
T
S
O
T
S
A
SLAVE
ADDRESS
A
SLAVE
AT
MASTER R ADDRESS
BYTE
R ADDRESS
CO
T
T
KP
S
S
P
SLAVE
A
A
C
C
K
K
A
C
K
DATA
BYTE
Figure 11. Sequential Read Sequence
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
A
A
A
C
C
C
K
K
K
SLAVE
A
C
DATA
K
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
N
O
S
AT
CO
KP
P
DATA
BYTE
n+x
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1118, Rev. A