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XRT7300IV

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation 

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PIN DESCRIPTION

PIN #

SYMBOL

27

EXCLK

28

GND

29

VDD

30

LCV/(RCLK2)

31

RCLK1

32

RNEG

33

RPOS

34

ICT

XRT7300

E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.1.1

TYPE

I

****

****

O

O

O

O

I

DESCRIPTION

External Reference Clock Input:

Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal

for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications.

Receiver Digital Ground

Receiver Digital VDD

Line Code Violation Indicator/Receive Clock Output pin 2:

The function of this pin depends upon whether the XRT7300 is operating in the

HOST Mode, the Hardware Mode or User selection.

HOST Mode - Line Code Violation Indicator Output:

If the XRT7300 is configured to operate in the HOST Mode, then this pin func-

tions as the LCV output pin by default. However, by using the on-chip Command

Registers, this pin can be configured to function as the second Receive Clock

signal output pin (RCLK2).

Hardware Mode - Receive Clock Output pin 2:

This output pin is the Recovered Clock signal from the incoming line signal. The

receive section of the XRT7300 outputs data via the RPOS and RNEG output

pins on the rising edge of this clock signal.

NOTE: If the XRT7300 is operating in the HOST Mode and this pin is configured

to function as the additional Receive Clock signal output pin, then the XRT7300

can be configured to update the data on the RPOS and RNEG output pins on the

falling edge of this clock signal.

Receive Clock Output pin 1:

This output pin is the Recovered Clock signal from the incoming line signal. The

receive section of the XRT7300 outputs data via the RPOS and RNEG output

pins on the rising edge of this clock signal.

NOTE: If the XRT7300 device is operating in the “Host” Mode, then the user can

configure the device to update the data on the RPOS and RNEG output pins on

the falling edge of this clock signal.

Receive Negative Pulse Output:

This output pin pulses “High” whenever the XRT7300 has received a Negative

Polarity pulse in the incoming line signal at the RTIP/RRING inputs.

NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-

terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not

reflected at this output.

Receive Positive Pulse Output:

This output pin pulses “High” whenever the XRT7300 has received a Positive

Polarity pulse in the incoming line signal at the RTIP/RRING inputs.

NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-

terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not

reflected at this output.

In-Circuit Test Input:

Setting this pin “Low” causes all digital and analog outputs to go into a high-

impedance state to allow for in-circuit testing. This pin is internally pulled “High”.

7

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