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HFA3861B

Direct Sequence Spread Spectrum Baseband Processor

Intersil 

HFA3861B

detected output is then processed through the differential

decoder to demodulate the last two bits of the symbol.

Data Demodulation and Tracking

Description (DBPSK and DQPSK Modes)

The signal is demodulated from the correlation peaks

tracked by the symbol timing loop (bit sync) as shown in

Figure 12. The frequency and phase of the signal is

corrected using the NCO that is driven by the phase locked

loop. Demodulation of the DBPSK data in the early stages of

acquisition is done by differential detection. Once phase

locked loop tracking of the carrier is established, coherent

demodulation is enabled for better performance. Averaging

the phase errors over 10 symbols gives the necessary

frequency information for proper NCO operation.

Configuration Register 10 sets the search timer for the SFD.

This register sets this time-out length in symbols for the

receiver. If the time out is reached, and no SFD is found, the

receiver resets to the acquisition mode. The suggested value is

the number of preamble symbols plus 16. If different transmit

preamble lengths are used by various transmitters in a network,

the longest value should be used for the receiver settings.

Data Decoder and Descrambler

Description

The data decoder that implements the desired DQPSK

coding/decoding as shown in Table 8. The data is formed

into pairs of bits called dibits. The left bit of the pair is the first

in time. This coding scheme results from differential coding

of the dibits. Vector rotation is counterclockwise for a positive

phase shift, but can be reversed with bit 7 or 6 of CR 1.

For DBPSK, the decoding is simple differential decoding.

TABLE 8. DQPSK DATA DECODER

PHASE SHIFT

DIBIT PATTERN (D0, D1)

D0 IS FIRST IN TIME

0

00

+90

01

+180

11

-90

10

The data scrambler and de-scrambler are self synchronizing

circuits. They consist of a 7-bit shift register with feedback of

some of the taps of the register. The scrambler is designed to

insure smearing of the discrete spectrum lines produced by the

PN code. One thing to keep in mind is that both the differential

decoding and the descrambling cause error extension or burst

errors. This is due to two properties of the processing. First, the

differential decoding process causes errors to occur on pairs of

symbols. When a symbol’s phase is in error, the next symbol

will also be decoded wrong since the data is encoded in the

change in phase from one symbol to the next. Thus, two errors

are made on two successive symbols. Therefore up to 4 bits

may be wrong although on the average only 2 are. In QPSK

mode, these may occur next to one another or separated by up

to 2 bits. In the CCK mode, when a symbol decision error is

made, up to 6 bits may be in error although on average only 3

bits will be in error. Secondly, when the bits are processed by

the descrambler, these errors are further extended. The

descrambler is a 7-bit shift register with two taps exclusive or’ed

with the bit stream. Thus, each error is extended by a factor of

three. Multiple errors can be spaced the same as the tap

spacing, so they can be canceled in the descrambler. In this

case, two wrongs do make a right. Given all that, if a single

error is made the whole packet is discarded anyway, so the

error extension property has no effect on the packet error rate.

Descrambling is self synchronizing and is done by a

polynomial division using a prescribed polynomial. A shift

register holds the last quotient and the output is the exclusive-

or of the data and the sum of taps in the shift register.

SAMPLES

AT 2X CHIP

RATE

CORRELATION

PEAK

CORRELATION TIME

T0

CORRELATOR OUTPUT IS

THE RESULT OF CORRELATING

THE PN SEQUENCE WITH THE

RECEIVED SIGNAL

T0 + 1 SYMBOL

CORRELATOR

OUTPUT

REPEATS

FIGURE 12. CORRELATION PROCESS

EARLY

ON-TIME

LATE

T0 + 2 SYMBOLS

16

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