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CS8402A-CP

Digital Audio Interface Transmitter

Cirrus Logic 

CS8401A

on flag 0 and flag 1 may cause an interrupt, the

falling edge of flag 2 will not.

Figure 11 illustrates the flag timing for an entire

channel status block which includes 24 bytes of

channel status data and 384 audio samples. (This

figure assumes the channel status bit is the same

for the audio pair.) The lower portion of Fig-

ure 11 expands the first byte of channel status

showing eight pairs of data with a pair defined

as a frame. This is further expanded showing the

first sub-frame (A0) to contain 32 bits as per the

AES/EBU specifications (see Appendix A).

When transmitting stereo, channel A is left and

channel B is right. The preamble at the bottom

of Figure 11 is expanded in Figure 15 to show

the exact timing between flags, the interrupt pin,

and internal buffer-read timing.

Buffer Mode 0

In buffer mode 0, in addition to the user-data

buffer previously discussed, one entire block of

channel status data is buffered in 24 memory lo-

cations from address 08H to 1FH. This block

will be transmitted in both channel A and chan-

nel B, one bit per frame. Like the user-data

buffer, the parallel port can access any location

in this buffer at any time. The transmitter section

reads this buffer in a cyclic non-destructive man-

ner and stores the byte in an 8-bit shift register

that is shifted once per two transmitted audio

samples (once per frame).

Flag 1 in the status register can be used to moni-

tor the channel status buffer. In mode 0, flag 1 is

set low when byte 0, location 08H, is read, and

set high when byte 16, location 18H, is read. If

mask 1 in control register 1 is set, a transition on

flag 1 will generate a pulse on the interrupt pin.

Figure 12 illustrates the memory read sequence

for buffer mode 0 along with the flag timing.

The arrows on the flags indicate an interrupt if

the appropriate mask bit is set. Flag 0 can cause

an interrupt on either edge, which is shown only

in the expanded portion of the Figure for clarity.

The expanded section also shows that the user

buffer is reread when location 0AH of the chan-

nel status is read.

Buffer Mode 1

In buffer mode 1, eight bytes are allocated for

channel status data and 16 bytes for auxiliary

data as shown in Figure 5. The channel status

buffer, locations 08H to 0FH, is divided into two

sections. The first four locations always contain

the first four bytes of channel status, identical to

Flag 2

Flag 1

Flag 0

C.S. Byte

C.S. Address

Block

(384 Audio Samples)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1

08

0B 0C

1F 08

(Expanded)

Flag 0

C.S. Address

User Address

08

09

0A

0B

(Addresses are in Hex)

04 05 06 07 04 05 06 07

Figure 12. CS8401A Buffer Memory Read Sequence - MODE 0

DS60F1

13

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