PSB4860 Просмотр технического описания (PDF) - Infineon Technologies
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PSB4860
Infineon Technologies
PSB4860 Datasheet PDF : 324 Pages
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PSB 4860
MA0-MA13
RAS
CAS0,CAS1
MD0-MD7
row addr.
t1
t2
col. addr.
t4
t3
t5
t6
t7 t8
Figure 88 Memory Interface - DRAM Read Access
Parameter
Memory Interface - DRAM Read Access
row address setup time
row address hold time
column address setup time
RAS precharge time
RAS to CAS delay
CAS pulse width
Data input setup time
Data input hold time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Limit values
Min
Max
50
50
50
110
110
2000
110
2000
40
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
311
2000-01-14
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