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TDA7500

DIGITAL AM/FM SIGNAL PROCESSOR

STMicroelectronics 

TDA7500

FUNCTIONAL DESCRIPTION.

The TDA7500 IC broken up into two distinct

blocks. One block contains the two DSP Cores

and their associated peripherals. The other con-

tains the ADC, DAC and the RDS filter, demodu-

lator and decoder.

24-BIT DSP CORE.

The two DSP cores are used to process the

audio and FM/AM data, coming from the ADC,

either any kind of digital data coming via SPDIF

or SAI. After the digital signal processing these

data are sent to the DAC for analog conversion.

Functions such as volume, tone, balance, and

fader control, as well as spatial enhancement and

general purpose signal processing may be per-

formed by the DSP0. When FM/AM mode is se-

lected, DSP1 is fully devoted to AM/FM process-

ing. Nevertheless it can be used for any kind of

different application, when a different input

source is selected.

Some capabilities of the DSPs are listed below:

Single cycle multiply and accumulate with con-

vergent rounding and condition code generation

2 x 56-bit Accumulators

Double precision multiply

Scaling and saturation arithmetic

48-bit or 2 x 24-bit parallel moves

64 interrupt vector locations

Fast or long interrupts possible

Programmable interrupt priorities and masking

8 each of Address Registers, Address Offset

Registers and Address Modulo Registers

Linear, Reverse Carry, Multiple Buffer Modulo,

Multiple Wrap-around Modulo address arith-

metic

Post-increment or decrement by 1 or by offset,

Index by offset, predecrement address

Repeat instruction and zero overhead DO

loops

Hardware stack capable of nesting combina-

tions of 7 DO loops or 15 interrupts/subrou-

tines

Bit manipulation instructions possible on all

registers and memory locations. Also Jump on

bit test.

4 pin serial debug interface

Debug ccess to all internal registers, buses

and memory locations

5 word deep program address history FIFO

Hardware and software breakpoints for both

program and data memory accesses

Debug Single stepping, Instruction injection

and Disassembly of program memory

DSP PERIPHERALS

There are a number of peripherals that are tightly

coupled to the two DSP Cores. Same of the pe-

ripherals are connected to DSP 0 others are con-

nected to DSP1.

512 x 24-Bit X-RAM.

512 x 24-Bit Y-RAM.

1024 x 24-Bit Program RAM (5.5K x 24 for

DSP1)

128 x 24-Bit Boot ROM for each DSP.

Serial Audio Interface (SAI)

SPDIF receiver with sampling rate conversion

I2C and SPI interface

XCHG Interface for DSP to DSP communica-

tion.

External Memory Interface (DRAM/SRAM) for

time-delay and traffic information.

Double Debug Port

DATA AND PROGRAM MEMORY

Both DSP0 and DSP1 have an identical set of

Data and Program memories attached to them.

Each of the memories are described below and it

is implied that there are two of each type, one set

connected to DSP0 and the other to DSP1. The

only exception is the case of the P-RAM where

DSP0 has a 1024 x 24-Bit PRAM and DSP1 has

a 5.5K x 24-Bit PRAM.

512 x 24-Bit X-RAM (XRAM)

This is a 512 x 24-Bit Single Port SRAM used for

storing coefficients. The 16-Bit XRAM address,

XABx(15:0) is generated by the Address Genera-

tion Unit of the DSP core. The 24-Bit XRAM Data,

XDBx(23:0), may be written to and read from the

Data ALU of the DSP core. The XDBx Bus is also

connected to the Internal Bus Switch so that it

can be routed to and from all peripheral blocks.

512 x 24 Bit Y-RAM (YRAM)

This is a 512 x 24-Bit Single Port SRAM used for

storing coefficients. The 16-Bit address,

YABx(15:0) is generated by the Address Genera-

tion Unit of the DSP core. The 24-Bit Data,

YDBx(23:0), is written to and read from the Data

ALU of the DSP core. The YDBx Bus is also con-

nected to the Internal Bus Switch so that it can be

routed to and from other blocks.

1024 x 24-Bit Program RAM (PRAM 5.5K x 24-bit

for DSP1)

This is a 1024 x 24-Bit Single Port SRAM used

for storing and executing program code. The 16-

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