WM8770 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

Номер в каталоге

Компоненты Описание

Список матч

WM8770

24-bit, 192kHz 8-Channel Codec with Volume Control

Wolfson Microelectronics plc 

Production Data

MASTER CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8770

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless

otherwise stated.

PARAMETER

System Clock Timing Information

MCLK System clock pulse width high

MCLK System clock pulse width low

MCLK System clock cycle time

MCLK Duty cycle

Power-saving mode activated

Normal mode resumed

SYMBOL

tMCLKH

tMCLKL

tMCLKY

TEST CONDITIONS

After MCLK stopped

After MCLK re-started

MIN

11

11

28

40:60

2

0.5

Table 1 Master Clock Timing Requirements

TYP

MAX

UNIT

1000

60:40

10

1

ns

ns

ns

µs

MCLK

cycle

Note: If MCLK period is longer than maximum specified above, DACs are powered down with internal digital audio filters

being reset. In this mode, all registers will retain their values and can be accessed in the normal manner through the

control interface. Once MCLK is restored, the DACs are automatically powered up.

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

ADCLRC

WM8770

CODEC DACLRC

DOUT

DIN1/2/3/4

4

DSP/

ENCODER/

DECODER

Figure 2 Audio Interface - Master Mode

w

PD Rev 4.1 June 2005

9

Share Link: