WM2633 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM2633

Byte-wide Parallel Input, 12-bit Voltage Output DAC with Internal Reference

Wolfson Microelectronics plc 

WM2633

Production Data

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V

supply current will increase.

9. Typical supply current in powerdown mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and

falling edges. Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with

a sampling frequency fS .

PARALLEL INTERFACE

D[0-7]

A[0-1]

NCS

NWE

NLDAC

X

X

tSUD

Data

tSUA

tSUCSWE

Address

tHD

X

tHA

X

tWWE

tSUWELD

tWLD

Figure 1 Timing Diagram

SYMBOL

tSUCSWE

tSUD

tHD

tSUA

tSUWELD

tWWE

tWLD

TEST

CONDITIONS

Setup time NCS low before positive NWE edge

Data ready before positive NWE edge

Data hold after positive NWE edge

Setup time for address bits A0, A1

Positive NWE edge before NLDAC low

High pulse width of NWE

Low pulse width of NLDAC

MIN TYP MAX UNIT

15

ns

10

ns

5

ns

20

ns

5

ns

20

ns

23

ns

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

6

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