W921E880 Просмотр технического описания (PDF) - Winbond

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W921E880

4-BIT MICROCONTROLLER

Winbond 

W921E880A/W921C880

The internal serial clock can be controlled by the serial clock speed control register (SRSPC) is

described as follows:

SRSPC register: (address = 00BH, default data = 0H)

b3

b2

b1

b0

b3 b2 b1 b0 Input frequency

0000

Reserved

0001

fsys/4 Hz

0010

fsys/8 Hz

0011

fsys/16 Hz

0100

fsys/32 Hz

0101

fsys/64 Hz

0110

fsys/128 Hz

0111

fsys/256 Hz

1000

fsys/512 Hz

1 0 0 1 fsys/1024 Hz

1 0 1 0 fsys/2048 Hz

Normally the WCLK or RCLK pin will remain in a high state and the serial data will be latched at the

rising edge of the WCLK or RCLK signal, but the serial clock inverter control register (SRINV) will

invert the above function. In this case the WCLK or RCLK pin will remain in a low state and the serial

data will be latched at the falling edge of the the WCLK or RCLK signal.

The transmitting serial clock can come from WCLK or RCLK depending upon which one is enabled. If

the serial function is disabled, it will cause the relative pins to be in a high impedance state and it will

not affect the contents of the serial buffer registers (start at address 050H).

6.7 DTMF Generator

One channel of the dual tone multi-frequency (DTMF) generator is in this chip. The exact frequency

must be decided by the OSCCTR REG to get the exact DTMF generator.

OSCCTR REG: (ADDRESS = 013H, Default data = 0H)

b3

b2

b1

b0

Reserved.

b2 b1 b0

000

001

010

011

100

101

Osc. Selection

400 KHz

800 KHz

2 MHz

4 MHz

Reserved

3.58MHz

There are four bits in the DTMF REG; the functions are described in the following table

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Publication Release Date: July 1999

Revision A3

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