W83194BR-648 Просмотр технического описания (PDF) - Winbond
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W83194BR-648 Datasheet PDF : 26 Pages
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W83194BR-648
7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT
PIN NO PWD
DESCRIPTION
7
15
1 PCICLK_F1 output control
6
14
1 PCICLK_F0 output control
5
23
1 PCICLK 5 output control
4
22
1 PCICLK 4 output control
3
21
1 PCICLK 3 output control
2
20
1 PCICLK 2 output control
1
17
1 PCICLK 1 output control
0
16
1 PCICLK 0 output control
7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT
PIN NO PWD
DESCRIPTION
7
27
1 48 MHZ output control
6
26
1 24_48 MHz output control
24/48 MHz frequency control
5
SEL_24
1 1: 24 MHz.
0: 48 MHz.
4
10
1 ZCLK1 output control
3
9
1 ZCLK0 output control
2
4
1 REF2 output control
1
3
1 REF1 output control
0
2
1 REF0 output control
7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH)
BIT
Pin NO PWD
DESCRIPTION
CPUCLKT/C0 Stop control: 0: CPUCLK0 free run
7
1
1: CPUCLK0 can stopped by CPU_STOP#
CPUCLKT/C1 Stop control: 0: CPUCLK1 free run
6
1
1: CPUCLK1 can stopped by CPU_STOP#
5
0 PCI_F0 Stop control: 0: PCI_F0 free run
1: PCI_F0 can stopped by PCI_STOP#
PCI_F1 Stop control: 0: PCI_F1 free run
4
0
1: PCI_F1 can stopped by PCI_STOP#
3
30
1 AGP_1 output control
2
31
1 AGP_0 output control
1 MULTISEL0 X MULTISEL0 trapping pin data read back, Default 1.
0 Reserved 0 Reserved
-8-
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