Preliminary W6691
2. FEATURES
• Full Duplex 2B+D S/T interface transceiver compliant with ITU I.430 Recommendation
• One D channel HDLC controller
- Maskable address recognition
- Transparent (HDLC) mode
- FIFO buffer (2 * 64)
• Two B channel HDLC controller
- Maskable address recognition
- Transparent (HDLC) mode
- FIFO buffer (2 * 128)
• Various B channel switching capabilities and PCM intercom
• Two PCM CODEC interfaces for speech and POTS application
• GCI interface connects with other peripheral device in TE, LT-S and LT-T mode.
• Multi-frame synchronization
• 8-bits Intel mode or Motorola mode interface accesses B channel and Command/Indication channel.
• The timing clock recovery depends on operating mode.
• DPLL circuit designed in chip for NT2 application.
• Four kind of the extended interrupt trigger mode.
• Two kind of output interrupt polarity selection can be programmed.(Positive level and negative Level)
• Added reset signal to reset other chip.
• Loop back function for testing.
• Layer1 Activate Indication Output can be connected to LED
• Two of programmable timer
• 3.3 Volt power supply
• 3.3 Volt output; Maximum Input is 5.0Volt
• Advanced CMOS technology
• 64 pin LQFP or 68 pin PLCC package
Publication Release Date: Sep 2001
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Revision 1.1