W6691CD Просмотр технического описания (PDF) - Winbond
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W6691CD Datasheet PDF : 106 Pages
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Preliminary W6691
8.5 GCI Bus Register Memory Map........................................................................................................ 57
8.6 Miscellaneous Register Memory Map .............................................................................................. 58
Table 8.6 Miscellaneous Register Memory Map .................................................................................... 58
8.7 D channel HDLC Controller Register Description............................................................................. 58
8.7.1 D_ch receive FIFO D_RFIFO Read Address 00H......................................................................58
8.7.2 D_ch transmit FIFO D_XFIFO Write Address 01H.....................................................................59
8.7.3 D_ch command register D_CMDR Write Address 02H .............................................................59
8.7.4 D_ch Mode Register D_MODE Read/Write Address 03H ..........................................................60
8.7.5 Interrupt Status Register ISTA Read_clear Address 04H.......................................................61
8.7.6 Interrupt Mask Register IMASK Read/Write Address 05H...........................................................63
8.7.7 D_ch Extended Interrupt Register D_EXIR Read_clear Address 06H .......................................63
8.7.8 D_ch Extended Interrupt Mask Register D_EXIM Read/Write Address 07H...............................64
8.7.9 D_ch Transmitter Status Register D_XSTA Read Address 0AH..............................................65
8.7.10 D_ch Receive Status Register D_RSTA Read Address 0BH ................................................65
8.7.11 D_ch SAPI Address Mask D_SAM Read/Write Address 0EH ................................................66
8.7.12 D_ch SAPI1 Register D_SAP1 Read/Write Address 0FH........................................................67
8.7.13 D_ch SAPI2 Register D_SAP2 Read/Write Address 10H ........................................................67
8.7.14 D_ch TEI Address Mask D_TAM Read/Write Address 11H ....................................................67
8.7.15 D_ch TEI1 Register D_TEI1 Read/Write Address 12H..........................................................68
8.7.16 D_ch TEI2 Register D_TEI2 Read/Write Address 13H..........................................................68
8.7.17 D_ch Receive Frame Byte Count High D_RBCH Read Address 16H .....................................69
8.7.18 D_ch Receive Frame Byte Count Low D_RBCL Read Address 17H....................................69
8.8 GCI Bus Register Description........................................................................................................... 70
8.8.1 Channel Selection Register CSEL Read/Write Address 18H ................................................70
8.8.2 Command/Indication Receive Register CIR Read Address 1AH...............................................70
8.8.3 Command/Indication Transmit Register CIX Read/Write Address 1BH ...................................71
8.8.4 S/Q Channel Receive Register SQR Read Address 1CH ...........................................................71
8.8.5 S/Q Channel Transmit Register SQX Read/Write Address 1DH ...............................................72
8.8.6 Monitor Receive Channel 0 MO0R Read Address 20H..........................................................72
8.8.7 Monitor Transmit Channel 0 MO0X Read/Write Address 21H................................................72
8.8.8 Monitor Channel 0 Interrupt Register MO0I Read_clear Address 22H .................................73
8.8.9 Monitor Channel 0 Control Register MO0C Read/Write Address 23H .....................................73
8.8.10 GCI Mode Control/Status Register GCR
Read Address 26H .....................................74
8.8.11 Monitor Receive Channel 1 Register MO1R Read Address 27H ...........................................75
8.8.12 Monitor Transmit Channel 1 Register MO1X
Read/Write Address 28H.......................75
8.8.13 Monitor Channel 1 Interrupt Register MO1I Read_clear Address 29H ...............................76
8.8.14 Monitor Channel 1 Control Register MO1C Read/Write Address 2AH ....................................76
8.8.14 GCI CI1 Indication Register CI1R Read Address 31H ........................................................77
Publication Release Date: Sep 2001
3
Revision 1.1
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