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6. BLOCK DIAGRAM
The block diagram of W6691 is shown in Figure 6.1
Preliminary W6691
4-wire S/T
Line
Transceiver
&
AMI/BIN
Conversion
2B+D
2B+D
Slip
Buffer
GCI Bus
B-channel Switching
GCI Bus
GCI
Circuit
2B+D
Crystal/Oscillator
(7.68 MHz)
POTS
circuit
DPLL1 and Timing Generator
I/O Control
FSCO
DCLO
C16.384
D
HDLC
Controller
B1
HDLC
Controller
B2
HDLC
Controller
PCM
Port
FIFO
FIFO
FIFO
DPLL2
Microprocessor
Interface Circuit
PCM CODEC
Fig.6.1 W6691 Functional Block Diagram
Publication Release Date: Sep 2001
18
Revision 1.1