W40S11-23G(1999) Просмотр технического описания (PDF) - Cypress Semiconductor
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W40S11-23G Datasheet PDF : 9 Pages
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W40S11-23
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 2 gives the bit formats for registers located in Data Bytes
0–6.
Table 2. Data Bytes 0–2 Serial Configuration Map[2]
Affected Pin
Bit(s)
Pin No.
Pin Name
Control Function
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
11
SDRAM5 Clock Output Disable
6
10
SDRAM4 Clock Output Disable
5
N/A
Reserved (Reserved)
4
N/A
Reserved (Reserved)
3
7
SDRAM3 Clock Output Disable
2
6
SDRAM2 Clock Output Disable
1
3
SDRAM1 Clock Output Disable
0
2
SDRAM0 Clock Output Disable
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
27
SDRAM11 Clock Output Disable
6
26
SDRAM10 Clock Output Disable
5
23
SDRAM9 Clock Output Disable
4
22
SDRAM8 Clock Output Disable
3
N/A
Reserved (Reserved)
2
N/A
Reserved (Reserved)
1
19
SDRAM7 Clock Output Disable
0
18
SDRAM6 Clock Output Disable
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
N/A
Reserved (Reserved)
6
12
SDRAM12 Clock Output Disable
5
N/A
Reserved (Reserved)
4
N/A
Reserved (Reserved)
3
N/A
Reserved (Reserved)
2
N/A
Reserved (Reserved)
1
N/A
Reserved (Reserved)
0
N/A
Reserved (Reserved)
Bit Control
0
1
Low
Active
Low
Active
-
-
-
-
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
-
-
-
-
Low
Active
Low
Active
-
-
Low
Active
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Note:
2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to a “0.”
3
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