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KT133A - VT8363A
• Advanced High-Performance DRAM Controller
− Supports PC133 and PC100 SDRAM and Virtual Channel Memory (VCM) SDRAM up to 3 DIMMs
− Concurrent CPU, AGP, and PCI access
− Different DRAM types may be used in mixed combinations
− Different DRAM timing for each bank
− Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
− Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs
− Support up to 1.5 GB memory space (256Mb DRAM technology)
− Flexible row and column addresses
− 64-bit data width and 3.3V DRAM interface
− Programmable I/O drive capability for MA, command, and MD signals
− Two-bank interleaving for 16Mbit SDRAM support
− Two-bank and four bank interleaving for 64Mbit SDRAM support
. − Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU
− Independent SDRAM control for each bank
− Seamless DRAM command scheduling for maximum DRAM bus utilization
# (e.g., precharge other banks while accessing the current bank)
+ − Four cache lines (32 quadwords) of CPU to DRAM write buffers
− Four cache lines (32 quadwords) of CPU to DRAM read prefetch buffers
6 − Read around write capability for non-stalled CPU read
− Burst read and write operation
− BIOS shadow at 16KB increment
− Decoupled and burst DRAM refresh with staggered RAS timing
0 − CAS before RAS or self refresh
' & • Advanced System Power Management Support
− Dynamic power down of SDRAM (CKE)
& ' − PCI and AGP bus clock run and clock generator control
− VTT suspend power plane preserves memory data
− Suspend-to-DRAM and Self-Refresh operation
+ 4 − SDRAM self-refresh power down
− 8 bytes of BIOS scratch registers
( + − Low-leakage I/O pads
• Built-in NAND-tree pin scan test capability
0 7 • 3.3V, 0.35um, high speed / low power CMOS process
1 '3 • 35 x 35 mm, 552 pin BGA Package
Preliminary Revision 0.1, October 9, 2000
-3-
Features