VRS51L1050-25-P-ISPV3 Просмотр технического описания (PDF) - Ramtron International Corporation
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VRS51L1050-25-P-ISPV3
Ramtron International Corporation
VRS51L1050-25-P-ISPV3 Datasheet PDF : 49 Pages
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VRS51L1050
Internal SRAM Control Register
The 768 bytes of expanded SRAM can also be
accessed using the MOVX @Rn instruction (where n =
0 or 1). This instruction can only access data in a
range of 256 bytes. The internal SRAM control register
(RCON) allows users to select which part of the
expanded SRAM will be accessed by this instruction,
by configuring the value of the RAMS0 and RAMS1
bits.
The default setting of the RAMS1 and RAMS0 bits is
00 (page 0). Each page has 256 bytes.
TABLE 13: INTERNAL SRAM CONTROL REGISTER (RCON) - SFR 85H
7
6
5
4
3
2
1
Unused
RAMS1
0
RAMS0
Bit Mnemonic Description
7 Unused
-
6 Unused
-
5 Unused
-
4 Unused
-
3 Unused
-
2 Unused
-
1 RAMS1
These two bits are used with Rn of instruction
0 RAMS0
OVX @Rn, n=1,0 for mapping (see section on
extended 768 bytes)
RAMS1, RAMS0 Mapped area
00
000h-0FFh
01
100h-1FFh
10
200h-2FFh
11
XY00h-XYFF*
*Externally generated
Example:
Suppose that RAMS1, RAMS0 are set to 0 and 1,
respectively, and Rn has a value of 45h.
Performing MOVX @Rn, A, (where n is 0 or 1) allows the
user to transfer the value of A to the expanded SRAM at
address 145h (page 1).
Note that when both RAMS1 and RAMS0 are set to 1,
the value of P2 defines the upper byte and Rn defines
the lower byte of the external address. In this case, the
device will access the off-chip memory in the external
memory space using the external memory control
signals. Off-chip peripherals can, therefore, be mapped
into the “P2value”00h to “P2value”FFh address range.
Description of Peripherals
System Control Register
The following table describes the system control
register (SYSCON).
TABLE 14: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7 65
4
3
2
1
PDWAKEUP
IAPE XRAME
0
ALEI
Bit Mnemonic Description
7
Unused
-
6
Unused
-
5
Unused
-
4
PDWAKEUP Power down wakeup from INT0/INT1
0 = Deactivated
1 = Device can exit power down from the
external interrupt
3
Unused
-
2
IAPE
IAP function enable bit
0 = IAP function is deactivated
1 = IAP function is activated
1
XRAME
768 byte on-chip enable bit
0 = Enabled
1 = Disabled
0
ALEI
ALE output inhibit bit, which is used to
reduce EMI.
0 = ALE pin is active
1 = ALE is inhibited
Bit 4 of the SYSCON register is the PDWAKEUP bit
that, when set to 1, allows the device to exit power
down mode from external interrupt INT0/INT, provided
it is activated. If the PDWAKEUP bit is cleared, the
external INT0/INT1 will not wake up the processor.
The IAPE bit is used to enable and disable the IAP
function.
The XRAME bit allows the user to enable the on-chip
expanded 768 bytes of SRAM by setting the XRAME
bit to 1. By default, upon reset the XRAME bit is set to
0.
Bit 0 of the SYSCON register is the ALE output inhibit
bit. Setting this bit to 1 will inhibit the Fosc/6 clock
signal output to the ALE pin.
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