0
CLK
SI11..0
SYNC
34
CLK
SO15..0
OE
1
2
3
4
5
6
tPWH
tPWL
tCY
1
2
3
4
5
6
tS tH
35
1
36
37
tD
2
3
38
39
tOH
4
5
40
6
7
tDIS
7
tEN
Fig. 12 Timing Diagram - Decimation INT = 1, DEC = 1, SYNC = SYNC
tEN
OE
tDIS
0.5V
THREE STATE
OUTPUTS
HIGH IMPEDANCE
2.0V
0.8V
0.5V
Fig. 13 Threshold Levels for Three State Measurement
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright January 1995 Gennum Corporation. All rights reserved. Printed in Canada.
11
521 - 26 - 02