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V62C1161024L

Ultra Low Power 64K x 16 CMOS SRAM

Mosel Vitelic Corporation  

V62C1161024L(L)

Data Retention Characteristics (L Version Only)(1)

Parameter

VCC for Data Retention

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time(2)

Symbol

V DR

I CCDR

t CDR

tR

Test Condition

CE > VCC - 0.2V

L

VIN >VCC - 0.2V or

VIN < 0.2V

Min

1.0

-

0

tRC

Max

-

5

1

-

-

Unit

V

µA

ns

ns

Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)

VCC

CE

Vcc_typ

tCDR

VIH

Data Retention Mode

VDR > 1.0V

VDR

Vcc_typ

tR

VIH

Notes

1. L-version includes this feature.

2. This Parameter is sampled and not 100% tested.

3. For test conditions, see AC Test Condition, Figure A.

4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is High for read cycle.

7. CE and OE are LOW for read cycle.

8. Address valid prior to or coincident with CE transition LOW.

9. All read cycle timings are referenced from the last valid address to the first transtion address.

10. CE or WE must be HIGH during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

8

REV. 1.1 April 2001 V62C1161024L(L)

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