V370PDC(2000) Просмотр технического описания (PDF) - QuickLogic Corporation

Номер в каталоге

Компоненты Описание

Список матч

V370PDC
(Rev.:2000)

HIGH PERFORMANCE PCI TARGET INTERFACE with Integrated SDRAM Controller

QuickLogic Corporation 

V370PDC

Fully compliant with PCI Local Bus

Specification, Revision 2.2

Fully compliant with PCI Bus Power

Management Interface Specification,

Revision 1.0

Hot Swap Ready™ implemented

according to the Hot Swap

Specification, PICMG® 2.1

Up to 66 MHz local bus clock with

separate asynchronous PCI clock up

to 50 MHz

Large on-chip FIFO with Dynamic

Bandwidth Allocation™ architecture

On-the-fly byte order (endian)

conversion, including automatic byte

swapping

Up to 1 Kbyte of continuous burst

access to (E)SDRAM from PCI

Supports multiplexed and non-

multiplexed 8-, 16-, and 32-bit

generic local buses

Integrated SDRAM Controller

• Supports up to 1 Gbyte of

(E)SDRAM

• Support for up to 2 single-bank

168-pin SDRAM DIMMs

Buffered PCI clock output

Initialization through PCI or optional

serial EEPROM

Programmable PCI and local interrupt

management

Up to 5 programmable chip selects/

peripheral device strobe generation

Two 32-bit general purpose timers

3.3 V operation with 5 V tolerant

input

Industrial temperature range

(−40°C to +85°C)

160-pin PQFP package

HIGH PERFORMANCE

PCI TARGET INTERFACE

with Integrated SDRAM Controller

The V370PDC from V3 Semiconductor is a high-performance PCI target interface device

with an integrated SDRAM controller. It enables easy migration of legacy designs into

PCI designs, and it reduces design time and time-to-market on new PCI and CompactPCI

products. The V370PDC reduces overall system cost by replacing many lower integration

support components with a single, highly-integrated device.

High Performance PCI Target Solution

The V370PDC is fully compliant with the PCI Specification 2.2, supporting a 66 MHz

local bus clock with a separate asynchronous PCI clock up to 50 MHz. A large on-chip

FIFO featuring Dynamic Bandwidth Allocation™ architecture significantly reduces access

latencies by allowing the on-chip buffers to be more fully used. There are four PCI apertures

directed through FIFO buffers that are designed to maximize the bus.

Simple Implementation of High Availability Systems

CompactPCI applications in high availability systems will benefit from the PICMG® Hot

Swap Ready™ feature implemented by the V370PDC. By employing custom PCI buffers

to provide the necessary bias voltage, the V370PDC eliminates the need for numerous

external components to implement full Hot Swap Ready™ features.

Reduce System Cost

The V370PDC controls the essential components of an embedded system—SDRAM, flash,

and peripherals—by using an integrated memory controller and a peripheral control unit.

The V370PDC also provides additional peripheral functions, including timers, an interrupt

controller, and chip select logic. Integration of these functions into a low-cost, 160-pin

PQFP package reduces system cost by minimizing external components, maximizing board

space, and lowering manufacturing cost.

Share Link: