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USS-820FD

USB Device Controller

Agere -> LSI Corporation 

Data Sheet, Rev. 1

August 2004

USS-820FD

USB Device Controller

Register Timing Characteristics

All register timing specifications assume a 100 pF load on the D[7:0] package pins and a 70 pF load on all other

package pins.

Table 4. Timing Parameters

Symbol

tCLK

tRST

Internal Clock Period.

RESET Assert Time.

Parameter

Min Max Unit

—

83.3

ns

500

—

ns

Table 5. Register Access Timing—Special Function Register (SFR) Read

Symbol

Parameter

Min Max Unit

tRDASU

Read Address Setup Time. Starts before the trailing edge of

RDN or IOCSN, whichever is first.

60

—

ns

tRDAHD Read Address Hold. Starts after the trailing edge of RDN or

IOCSN, whichever is first:

Operational

−10

—

ns

Suspended

−1

—

ns

tRDDV1, Read Data Valid. From the leading edge of RDN or IOCSN or

tRDDV2 from address valid, whichever is last, to data valid:

Operational

—

74

ns

Suspended

—

33

ns

tRDDZ

Read Data to Z State. Starts after the trailing edge of RDN or

IOCSN, whichever is first.

2

32

ns

tRDREC Recovery Time Between Reads. From the trailing edge of RDN 23

—

ns

or IOCSN, whichever is first, to the next leading edge of RDN or

IOCSN, whichever is last.

tRDRECRXD Recovery Time Between Consecutive RXDAT Reads. From the 86

—

ns

trailing edge of RDN or IOCSN, whichever is first, to the next

trailing edge of RDN or IOCSN, whichever is first.

tRDPW Minimum Pulse Width. From the leading edge of RDN or

23

—

ns

IOCSN, whichever is last, to the trailing edge of RDN or IOCSN,

whichever is first.

IOCSN

tRDPW

RDN

A

D HIGH IMPEDANCE

tRDDV1

tRDASU

VALID

tRDDV2

VALID

tRDRECRXD

tRDREC

tRDAHD

tRDDZ

Agere Systems Inc.

Figure 5. Register Access Timing—SFR Read

VALID

VALID

5-5352

9

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