μPD43256B-X
Write Cycle Timing Chart 2 (/CS Controlled)
Address (Input)
/CS (Input)
/WE (Input)
tWC
tAS
tCW
tAW
tWP
tWR
I/O (Input)
High impedance
tDW
Data in
tDH
High
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M11012EJ6V0DS
13