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74ALS157

Data selector/multiplexer

Philips Electronics 

Philips Semiconductors

Data selector/multiplexer

Product specification

74ALS157/74ALS158

74ALS157 Quad 2-input data selector/multiplexer, non-inverting

74ALS158 Quad 2-input data selector/multiplexer, inverting

DESCRIPTION

The 74ALS157 is a quad 2-input multiplexer which selects 4 bits of

data from one of two sources under the control of a common select

input (S). The enable input (E) is active when Low. When E is High,

all of the outputs (Yn) are forced Low regardless of all other input

conditions.

Moving data from two registers to a common output bus is a typical

use of the 74ALS157. The state of the select input determines the

particular register from which data comes.

The device is the logic implementation of 4-pole, 2-position switch

where the position of the switch is determined by the logic levels

supplied to the select input. The 74ALS158 is similar but has

inverting outputs (Yn).

TYPE

TYPICAL

PROPAGATION DELAY

74ALS157

74ALS158

6.0ns

6.0ns

TYPICAL

SUPPLY CURRENT

(TOTAL)

6mA

6mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

16-pin plastic DIP

74ALS157N, 74ALS158N

16-pin plastic SO

74ALS157D, 74ALS158D

DRAWING

NUMBER

SOT38-4

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74ALS (U.L.)

HIGH/LOW

Ina, Inb, Inc, Ind

Data inputs

1.0/1.0

S

Select input

1.0/1.0

E

Enable input

1.0/1.0

Ya – Yd, Ya – Yd

Data outputs

20/240

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOAD VALUE

HIGH/LOW

20µA/0.1mA

20µA/0.1mA

20µA/0.1mA

0.4mA/24mA

PIN CONFIGURATION – 74ALS157

PIN CONFIGURATION – 74ALS158

S1

I0a 2

I1a 3

Ya 4

I0b 5

I1b 6

Yb 7

GND 8

16 VCC

15 E

14 I0d

13 I1d

12 Yd

11 I0c

10 I1c

9 Yc

LOGIC SYMBOL – 74ALS157

2 3 5 6 11 10 14 13

I0a I1a I0b I1b I0c I1c I0d I1d

1

S

15

E

Ya Yb Yc Yd

VCC = Pin 16

GND = Pin 8

4 7 9 12

SC00051

SC00053

S1

I0a 2

I1a 3

Ya 4

I0b 5

I1b 6

Yb 7

GND 8

16 VCC

15 E

14 I0d

13 I1d

12 Yd

11 I0c

10 I1c

9 Yc

LOGIC SYMBOL – 74ALS158

2 3 5 6 11 10 14 13

I0a I1a I0b I1b I0c I1c I0d I1d

1

S

15

E

Ya Yb Yc Yd

VCC = Pin 16

GND = Pin 8

4 7 9 12

SC00052

SC00054

1991 Feb 08

2

853–1129 01670

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