CS4630 Просмотр технического описания (PDF) - Cirrus Logic
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CS4630 Datasheet PDF : 38 Pages
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CS4630
INDEPENDENT TIMING ENVIRONMENT (TA = 0 to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD =
2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; XTALI = 12.288 MHz; unless otherwise noted)
Parameter
SCLK output cycle time
FSYNC output cycle time (@SCLK falling edge)
SCLK falling to FSYNC transition
LRCLK output cycle time (@ SCLK rising edge)
SCLK rising to LRCLK transition
SCLK falling to SDOUT/SDO2/SDO3 valid
SDIN/SDIN2 valid to SCLK rising (SI1F2-0: 010, SI2F1-0: 00)
SDIN/SDIN2 hold after SCLK rising
(SI1F2-0: 010, SI2F1-0: 00)
SDIN/SDIN2 valid to SCLK falling
(SI1F2-0: 011, SI2F1-0: 01)
SDIN/SDIN2 hold after SCLK falling
(SI1F2-0: 011, SI2F1-0: 01)
XTAL frequency
XTALI high time
(Note 4)
XTALI low time
(Note 4)
MCLK output frequency
(Note 4)
Symbol
tsclk
tfsync
tpd7
tlrclk
tpd8
tpd9
ts6
th6
ts7
th7
Min Typ Max
312 326
-
20000 20833
-
-45
2
45
20000 20833
-
-45
2
45
-
2
45
30
-
-
30
-
-
30
-
-
30
-
-
12.287
35
35
12.287
12.288
-
-
12.288
12.289
-
-
12.289
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
MHz
tsclk
SCLK
tpd7
FSYNC
t pd8
LRCLK
t fsync
t lrclk
SDOUT/SD02/SD03
tpd9
15
0
15
0
SDIN/SDIN2
ts7
ts6
17 16
0
th6
17 16
0
SDIN/SDIN2
19 18
0
19 18
0
th7
Figure 5. Independent Timing Configuration
10
DS445PP1
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