FM3570 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FM3570
Fairchild Semiconductor
FM3570 Datasheet PDF : 8 Pages
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OVRD
0
0
1
1
1
1
1
MUXSEL
0
1
0
0
0
0
1
MX SB
X
X
1
0
1
0
Note 2
MX SA
X
X
0
0
1
1
Note 1
Mux_ No n_mux_
outputs
ouput
all 0’s
all 0’s
Mux_
latched
inputs
NMO
(see Note 1)
Mux_
latched
inputs
NMO
(see Note 1)
From
From No n-
Non-
volatile
volatile
register
register
(SOPR A)
(S OPRA)
Donot use this
c ombination
From
From No n-
Non-
volatile
volatile
register
register
(S OPRB)
(SOPR B)
Mux_i From No n-
nputs
volatile
register
(SOPRA or
SOPRB )
Note 1: Latched NMO state will be the value present on the NMO output at the time
of the MUXSEL input transitioning from logic 0 to logic 1 state.
Note 2: Output depends on previously selected state of MXSB and MXSA bits
written to device.
Multiplexer Logic
The output multiplexer logic determines what value is actually
output to the Y-port. The value that it output is dependent upon
b7-b6 of the SOPRA and SOPRB registers, as well as the
external MUXSEL and OVRD inputs. There is only one set of
MXS bits in the SOPRA and SOPRB registers. Regardless of
whether one writes to SPRA or SOPRB register for setting the
MXS bits, the result is the same. These same bits appear in
both the registers. If the MUXSEL is logic 0 and OVRD is logic
1, then, if b7, b6 is “10” then the value on the I-port is passed.
when b7 is “00” the value of the SOPRA register is passed on
the next IIC stop condition, and when b7 is “01” the value of the
SOPRB register is passed on the next IIC stop condition. If
MUXSEL is logic 1 and OVRD is logic 1, the input lines I0-4 are
used to drive the outputs. The above table describes all the
combinations.
IIC Interface
The IIC Interface is a standard slave interface. As a slave interface
the device will not generate its own clock. Data can be read from
and written into the device. Commands for reading and writing the
registers are generated by the IIC Master.
START and STOP Conditions
SDA
SCL
START
Condition
STOP
Condition
Figure 2. START & STOP Conditions
The IIC protocol uniquely defines START and STOP conditions.
A START condition is defined as a HIGH to LOW transition of the
SDA signal while SCL is HIGH. A STOP condition is defined as a
LOW to HIGH transition of the SDA signal while SCL is HIGH.
These are shown in Figure 2.
Device Addressing
The device uses 7-bit IIC addressing.The address has been
defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the
ASEL input is ‘0’. The address byte is the first byte of data sent after
a start condition. This is the only address that this device will
respond to. The device will not respond to the general call address
0000 000.
Reading from the Registers
Data can be read from both of the internal registers. All reads are non-
destructive and do not change the value in the register or the internal
state of the device. When a start condition is received with a read
request, both registers can be read out in the following sequence:
(1) SOPRA: Serial Output Port Register A
(2) SPORB: Serial Output Port Register B
(3) PIPR: PORT-I Value
If so desired, only the SOPRA register can be read. This is
accomplished by issuing a stop command after the acknowledge
bit for the first byte is read. If no stop is issued, the device will output
the registers in the above sequence.
Writing to the Registers
Data is written to the SOPR registers through the serial port
interface. When a write request is received with the Start Address
it is assumed that the intent is to write to the SOPR registers. The
value placed in the least 6 significant bits of the register contain the
new code to be placed in the SOPR A/B registers. The value of the
two most significant bits must contain the address of the destina-
tion register SOPRA or SOPRB.
The internal non-volatile latch takes about 10 ms to update its data.
The new data is reflected on the outputs after the internal non-volatile
latch is updated, if the corresponding select bits (MXSx, OVRD and
MUXSEL) are set to reflect the state of the non-volatile register.
Register Read Sequence
Slave
SOPRA
SOPRB
PIPR
S Address R A Register A Register A Register A P
S 1001110 1 A 00bbbbbb A 00bbbbbb A 00bbbbbb A P
Register Write Sequence
Slave
SOPRx
S Address W A Register A S
S 1001110 0 A xxbbbbbb A S
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01
selects SOPRB
Register Write Sequence using
Repeated Start Condition
Slave
SOPRA
Slave
SOPRx
S Address R A Register A S Address W A Register A P
S 1001110 1 A 00bbbbbb A S 1001110 0 A xxbbbbbb A P
Figure 4
FM3570 Rev. A
4
www.fairchildsemi.com
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