U631H256XS Просмотр технического описания (PDF) - Simtek Corporation
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U631H256XS Datasheet PDF : 15 Pages
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U631H256XS
RECALL; SRAM operation cannot commence until
tRESTORE after VCC exceeds VSWITCH.
If the U631H256XS is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and VCC.
Hardware Protection
The U631H256XS offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE ope-
ration will be inhibited.
Low Average Active Power
The U631H256XS has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0044
13
Rev 1.0
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