TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
PARAMETER MEASUREMENT INFORMATION
SCL
t(BUF)
SDA
t(LOW)
t(R)
VIH
VIL
t(HDSTA)
t(HDDAT)
VIH
VIL
t(F)
t(HIGH) t(SUSTA)
t(SUDAT)
t(SUSTO)
P
S
S
P
Stop
Condition
Start
Condition
Start
Stop
t(LOWSEXT)
SCLACK
SCLACK
t(LOWMEXT)
t(LOWMEXT)
t(LOWMEXT)
SCL
SDA
Figure 1. Timing Diagrams
1
91
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
ACK by
TSL256x
Frame 1 SMBus Slave Address Byte
Frame 2 Command Byte
ACK by Stop by
TSL256x Master
Figure 2. Example Timing Diagram for SMBus Send Byte Format
1
91
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
ACK by
TSL256x
Frame 1 SMBus Slave Address Byte
NACK by Stop by
Master Master
Frame 2 Data Byte From TSL256x
Figure 3. Example Timing Diagram for SMBus Receive Byte Format
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r
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www.taosinc.com
Copyright E 2010, TAOS Inc.
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