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VPC324XD

Comb Filter Video Processor

Micronas 

ADVANCE INFORMATION

VPC 323xD, VPC 324xD

2.3.9. Luminance Notch Filter

If a composite video signal is applied, the color infor-

mation is suppressed by a programmable notch filter.

The position of the filter center frequency depends on

the subcarrier frequency for PAL/NTSC. For SECAM,

the notch is directly controlled by the chroma carrier

frequency. This considerably reduces the cross-lumi-

nance. The frequency responses for all three systems

are shown in Fig. 2–9.

dB

10

0

–10

–20

–30

–40

MHz

0

2

4

6

8

10

PAL/NTSC notch filter

dB

10

0

–10

–20

–30

–40

0

2

4

6

8

SECAM notch filter

Fig. 2–9: Frequency responses of the luma

notch filter for PAL, NTSC, SECAM

MHz

10

2.3.10. Skew Filtering

The system clock is free-running and not locked to the

TV line frequency. Therefore, the ADC sampling pat-

tern is not orthogonal. The decoded YCrCb signals are

converted to an orthogonal sampling raster by the

skew filters, which are part of the scaler block.

The skew filters are controlled by a skew parameter

and allow the application of a group delay to the input

signals without introducing waveform or frequency

response distortion.

The amount of phase shift of this filter is controlled by

the horizontal PLL1. The accuracy of the filters is 1/32

clocks for luminance and 1/4 clocks for chroma. Thus

the 4:2:2 YCrCb data is in an orthogonal pixel format

even in the case of nonstandard input signals such as

VCR.

2.4. Component Interface Processor CIP

This block (see Fig. 2–10) contains all the necessary

circuitry dedicated to external analogue components

(YCrCb_cip) such as RGB or YCrCb signals from DVD

players, or other RGB sources with Fast Blank for real

time insertion on the main picture (YCrCb_main).

2.4.1. Component Analogue Front End

VPC 32xxD provides two analogue RGB/YCrCb input

ports, one with Fast Blank capability and one without.

It is strongly recommended to use analogue 5 MHz

anti-alias low-pass filters on each input, including FB.

While all signals need to be capacitively coupled by

220 nF clamping capacitors, the Fast Blank input

requires DC coupling.

The selected signal channel is further converted into a

digital form by 3 high quality ADCs running at

20.25 MHz with a resolution of 8 bits. The FB input is

digitized with a resolution of 6 bits.

Note: The VPC32xxD system synchronization always

occurs through the main CVBS/Y ADC input. In any

component mode, this input must therefore be handled

accordingly.

2.4.2. Matrix

The RGB signals are converted to the YCrCb format by

a matrix operation:

Y = 0.299R + 0.587G + 0.114B

(R−Y)= 0.701R − 0.587G − 0.114B

(B−Y)=−0.299R − 0.587G + 0.886B

In case of YCrCb input the matrix is bypassed.

2.4.3. Component YCrCb Control

To guarantee optimum mixing results, various I2C pro-

grammable parameters are provided:

– 0 ≤ contrast ≤63/32

– −128 ≤ brightness ≤ 127

– 0 ≤ saturation Cr ≤ 63/32

– 0 ≤ saturation Cb ≤ 63/32

– −20 ≤ tint ≤ 20 degrees

Micronas

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