AD7713ARZ Просмотр технического описания (PDF) - Analog Devices
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AD7713ARZ Datasheet PDF : 28 Pages
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AD7713
TIMING CHARACTERISTICS1, 2 (DVDD = 5 V ؎ 5%; AVDD = 5 V or 10 V ؎ 5%; AGND = DGND = 0 V; fCLKIN = 2 MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Unit
Conditions/Comments
fCLK
3,
IN
4
tCLK IN LO
tCLK IN HI
tr5
tf5
t1
Self-Clocking Mode
t2
t3
t4
t5
t6
t76
t86
t9
t10
t14
t15
t16
t17
t18
t19
External-Clocking Mode
fSCLK
t20
t21
t22
t23
t246
t256
t26
t27
t28
t297
t30
t317
t32
t33
t34
t35
t36
400
2
0.4 ϫ tCLK IN
0.4 ϫ tCLK IN
50
50
1000
0
0
2 ϫ tCLK IN
0
4 ϫ tCLK IN + 20
4 ϫ tCLK IN +20
tCLK IN/2
tCLK IN/2 + 30
tCLK IN/2
3 ϫ tCLK IN/2
50
0
4 ϫ tCLK IN + 20
4 ϫ tCLK IN
0
10
fCLK IN/5
0
0
2 ϫ tCLK IN
0
4 ϫ tCLK IN
10
2 ϫ tCLK IN + 20
2 ϫ tCLK IN
2 ϫ tCLK IN
tCLK IN + 10
10
tCLK IN + 10
10
5 ϫ tCLK IN/2 + 50
0
0
4 ϫ tCLK IN
2 ϫ tCLK IN – SCLK High
30
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Master Clock Frequency: Crystal Oscillator or
Externally Supplied for Specified Performance
Master Clock Input Low Time; tCLK IN = 1/fCLK IN
Master Clock Input High Time
Digital Output Rise Time; Typically 20 ns
Digital Output Fall Time; Typically 20 ns
SYNC Pulse Width
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
Serial Clock Input Frequency
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to DRDY High
SCLK to Data Valid Hold Time
RFS/TFS to SCLK Falling Edge Hold Time
RFS to Data Valid Hold Time
A0 to TFS Setup Time
A0 to TFS Hold Time
SCLK Falling Edge to TFS Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 10 to 13.
3CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4The AD7713 is production tested with fCLK IN at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
REV. D
–5–
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